The present invention relates generally to signaling between electrical components and in particular the present invention relates to a mechanism to provide high resolution of signals transmitted in electrical systems.
In modern computer systems, signals from a common source may be distributed for controlling many widely separated circuit modules. The time delays associated with passage of a signal through parallel paths are not uniform; often, they arrive in skewed time relation to each other. Similarly, data transferred in parallel will often arrived skewed from adjacent data signals, or from an accompanying clock signal. Often, an attempt is made to correct the skew it by adding a finite time delay to the signal.
Within a computer system, data is passed from register to register, with varying amounts of processing performed between registers. Registers store data present at their inputs either at a system clock transition or during a particular phase of the system clock. Skew in the system clock signal impacts register-to-register transfers, i.e., it may cause a register to store data either before it has become valid or after it is no longer valid.
As system clock periods shrink there is increasing pressure on the computer architect to increase determinism in the system design. Clock skew, like setup time, hold time and propagation delay, increase the amount of time that data is in an indeterminable state. System designers must be careful that this indeterminable state does not fall within the sampling window of a register in order to preserve data integrity.
It is possible to minimize a limited amount of signal skew by applying careful attention to the layout and design of the circuit topography. Application of design rules to reduce skew becomes less effective as the clock period shrinks and the distance a signal must travel increases (at least with respect to the clock period). Many steps are only effective for the chips themselves and oftentimes cannot address skew from various divergent clock pulse path interconnections. In addition, such skew compensations, once implemented, oftentimes cannot accommodate introduction of subsequent increments of skew as from component aging, operating environment variations, and so forth.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a system and method of reducing skew between two or more signal lines.
The above mentioned problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment of the present invention, a delay line for adding delay to a signal is presented. The delay line includes a number of delay elements, including a first and a second delay element. The delay line further includes a multiplexer connected to each of the multiple of delay elements. According to the present invention the second delay element adds a predetermined delay to the signal and the first delay element operates with the multiplexer to selectively add a second predetermined delay to the signal.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.